Resolution
The resolution of the converter indicates the number of discrete values it can produce over the range of analog values. The values are usually stored electronically in binary form, so the resolution is usually expressed in bits. In consequence, the number of discrete values available, or "levels", is usually a power of two. For example, an ADC with a resolution of 8 bits can encode an analog input to one in 256 different levels, since 28 = 256. The values can represent the ranges from 0 to 255 (i.e. unsigned integer) or from -128 to 127 (i.e. signed integer), depending on the application.
Resolution can also be defined electrically, and expressed in volts. The voltage resolution of an ADC is equal to its overall voltage measurement range divided by the number of discrete intervals as in the formula:
Q = EFSR/2M = EFSR/N
Where:
Q is resolution in volts per step (volts per output code),
EFSR is the full scale voltage range = VRefHi − VRefLo,
M is the ADC's resolution in bits, and
N is the number of intervals, given by the number of available levels (output codes), which is: N = 2M
Some examples may help:
Example 1
Full scale measurement range = 0 to 10 volts
ADC resolution is 12 bits: 212 = 4096 quantization levels (codes)
ADC voltage resolution is: (10V - 0V) / 4096 codes = 10V / 4096 codes » 0.00244 volts/code 2.44 mV/code
Example 2
Full scale measurement range = -10 to +10 volts
ADC resolution is 14 bits: 214 = 16384 quantization levels (codes)
ADC voltage resolution is: (10V - (-10V)) / 16384 codes = 20V / 16384 codes » 0.00122 volts/code 1.22 mV/code
Example 3
Full scale measurement range = 0 to 8 volts
ADC resolution is 3 bits: 23 = 8 quantization levels (codes)
ADC voltage resolution is: (8 V − 0 V)/8 codes = 8 V/8 codes = 1 volts/code = 1000 mV/code
In practice, the smallest output code ("0" in an unsigned system) represents a voltage range which is 0.5X of the ADC voltage resolution (Q)(meaning half-wide of the ADC voltage Q ) while the largest output code represents a voltage range which is 1.5X of the ADC voltage resolution (meaning 50% wider than the ADC voltage resolution). The other N − 2 codes are all equal in width and represent the ADC voltage resolution (Q) calculated above. Doing this centers the code on an input voltage that represents the Mth division of the input voltage range. For example, in Example 3, with the 3-bit ADC spanning an 8 V range, each of the N divisions would represent 1 V, except the 1st ("0" code) which is 0.5 V wide, and the last ("7" code) which is 1.5 V wide. Doing this the "1" code spans a voltage range from 0.5 to 1.5 V, the "2" code spans a voltage range from 1.5 to 2.5 V, etc. Thus, if the input signal is at 3/8ths of the full-scale voltage, then the ADC outputs the "3" code, and will do so as long as the voltage stays within the range of 2.5/8ths and 3.5/8ths. This practice is called "Mid-Tread" operation. This type of ADC can be modeled mathematically as:
ADCCode = ROUND((2M/VRefHi - VRefLo)*(VIn - VRefLo))
The exception to this convention seems to be the Microchip PIC processor, where all M steps are equal width. This practice is called "Mid-Rise with Offset" operation.
ADCCode = FLOOR((2M/VRefHi - VRefLo)*(VIn - VRefLo))
In practice, the useful resolution of a converter is limited by the best signal-to-noise ratio that can be achieved for a digitized signal. An ADC can resolve a signal to only a certain number of bits of resolution, called the "effective number of bits" (ENOB). One effective bit of resolution changes the signal-to-noise ratio of the digitized signal by 6 dB, if the ADC limits the resolution. If a preamplifier has been used prior to A/D conversion, the noise introduced by the amplifier can be an important contributing factor towards the overall SNR.
Reference:
- http://en.wikipedia.org
