Using the Analog-to-Digital (A/D) Converter 3

Ratiometric Conversion
Ratiometric Conversion is the A/D conversion process in which the binary result is a ratio of the supply voltage or reference voltage, the latter being equal to full-scalevalue by default. The PIC16C7X is a ratiometric A/D converter where the result depends on VDD
or VREF. In some A/Ds, an absolute reference is provided resulting in “absolute conversion”.

Sample and Hold
In sample and hold type A/D converters, the analog input has a switch (typically a FET switch in CMOS) which is opened for a short duration to capture the analog input voltage onto an on-chip capacitor. Conversion is typically started after the sampling switch is closed.

Track and Hold
Track and Hold is basically the same as sample and hold, except the sampling switch is typically left on. Therefore the voltage on the on-chip holding capacitor “tracks” the analog input voltage. To begin a conversion, the sampling switch is closed. The PIC16C7X A/D falls in this category.

Sampling Time
Sampling Time is the time required to charge the on-chip holding capacitor to the same value as is on the analog input pin. The sampling time depends on the magnitude of the holding capacitor and the source impedance of the analog voltage input.

Offset Error (or Zero Error)
Offset Error is the difference between the first actual (measured) transition point and the first ideal transition point as shown in Figure 6. It can be corrected (by the user) by subtracting the offset error from each conversion result.

Full Scale Error (or Gain Error)
Full Scale Error is the difference between the ideal full scale and the actual (measured) full scale range (Figure 7). It is also called gain error, because the error changes the slope of the ideal transfer function creating a gain factor. It can be corrected (by the user) by multiplying each conversion result by the inverse of the gain.

Integral Non-Linearity (INL), or Relative Error
The deviation of a transition point from its corresponding point on the ideal transfer curve is called “Integral Non-Linearity” (Figure 8). The maximum difference is reported as the INL of the converter. It is important to note that Full Scale Error and the Offset Error are normalized to match end transition points before measuring the INL.

Reference:

1. AN546, Microchip Technology Inc. Sumit Mitra, Stan D’Souza, and Russ Cooper,

Using the Analog-to-Digital (A/D) Converter 2

Differential Non-Linearity (DNL)
It is the deviation in code-width from 1LSb (Figure 4). The difference is calculated for each and every transition. The largest difference is reported as DNL. It is important to note that the DNL is measured after the transfer function is normalized to match offset error and gain error. Note that the DNL cannot be any less than -1LSb. In the other direction, DNL can be >1LSb.

Absolute Error
The maximum deviation between any transition point from the corresponding ideal transfer function is defined as the absolute error. This is how it is measured and reported in the PIC16C7X (Figure 5). The notable difference between absolute error and integral non-linearity (INL) is that the measured data is not normalized for full scale and offset errors in absolute error. Absolute Error is probably the first parameter the user will review to evaluate an A/D. Sometimes absolute error is reported as the sum of offset, full-scale and integral non-linearity errors.

Total Unadjusted Error
Total Unadjusted Error is the same as absolute error. Again, sometimes it is reported as the sum of offset, full-scale and integral non-linearity errors.

No Missing Code
No missing code implies that as the analog input voltage is gradually increased from zero to full scale (or vice versa), all digital codes are produced. Stated otherwise, changing analog input voltage from one quantum of the analog range to the next adjacent range will not produce a change in the digital output by more than one code count.

Monotonic
Monotonicity guarantees that an increase (or decrease) in the analog input value will result in an equal or greater digital code (or less). Monotonicity does not guarantee that there are no missing codes. However, it is an important criterion for feedback control systems. Non-monotonicity may cause oscillations in such systems. The first derivative of a monotonic function always has the same sign.

Reference:

1. http://en.wikipedia.org
   
2. AN546, Microchip Technology Inc. Sumit Mitra, Stan D’Souza, and Russ Cooper,

Using the Analog to Digital Converter 1

INTRODUCTION

This application note is intended for PIC16C7X users with some degree of familiarity with analog system design. The various sections discuss the following topics:

• Commonly used A/D terminology
• How to configure and use the PIC16C71 A/D
• Various ways to generate external reference voltage (V REF)
• Configuring the RA3:RA0 pins
• 
  

COMMONLY USED A/D TERMINOLOGY

The Ideal Transfer Function

In an A/D converter, an analog voltage is mapped into an N-bit digital value. This mapping function is defined as the transfer function. An ideal transfer is one in which there are no errors or non-linearity. It describes the “ideal” or intended behavior of the A/D. Figure 1 shows the ideal transfer function for the PIC16C7X A/D.

Note that the digital output value is 00h for the analog input voltage range of 0 to 1LSb. In some converters, the first transition point is at 0.5LSb and not at 1LSb as shown in Figure 2. Either way, by knowing the transfer function the user can appropriately interpret the data.

Transition Point

The analog input voltage at which the digital output switches from one code to the next is called the “Transition Point.” The transition point is typically not a single threshold, but rather a small region of uncertainty (Figure 3). The transition point is therefore defined as

the statistical average of many conversions. Stated differently, it is the voltage input at which the uncertainty of the conversion is 50%.

Code Width

The distance (voltage differential) between two transition points is called the “Code Width.” Ideally the Code Width should be 1LSb (Figure 1).

Center of Code Width

The midpoint between two transition points is called the “Center of Code Width” (Figure 3).

Reference:

1. AN546, Microchip Technology Inc. Sumit Mitra, Stan D’Souza, and Russ Cooper,

ADC Definitions and Specifications 5

Integral Non-Linearity (INL)

Integral Non-Linearity (INL) is defined as the sum from the first to the current conversion
(integral) of the non-linearity at each code (Code DNL). For example, if the sum of the DNL up to a particular point is 1LSB, it means the total of the code widths to that point is
1LSB greater than the sum of the ideal code widths. Therefore, the current point will convert one code lower than the ideal conversion.

In more fundamental terms, INL represents the curvature in the Actual Transfer Function relative to a baseline transfer function, or the difference between the current and the ideal transition voltages. There are three primary definitions of INL in common use. They all have the same fundamental definition except they are measured against different transfer functions. This fundamental definition is:

Code INL = V(Current Transition) – V(Baseline Transition)
INL = Max(Code INL)

The three primary definitions are:

1. INL, Adjusted INL, or Endpoint INL — The current transition voltage is compared to the corresponding transition voltage on the Adjusted Transfer Function. This is a useful indicator of the best the ADC can do if the endpoint non-linearities (Zero- and Full-Scale Errors) are measured and trimmed out.
2. Unadjusted INL — The current transition voltage is compared to the corresponding transition voltage on the Ideal Transfer Function. This is a measure of the total error except for Quantization Error.
3. Best-Fit INL — The current transition voltage is compared to the corresponding transition voltage on the Best-Fit Transfer Function. This will usually give a balanced positive and negative error across the entire curve so the results look very optimistic, but since it is difficult to obtain the Best-Fit Transfer Function in application, it is not a very useful measure. Unfortunately, this is what many evaluation packages (hardware and software) measure.

There are some related definitions to Total Unadjusted Error that vary slightly in definition. These are:

1. Total Error is the same as Total Unadjusted Error, but the term is misused in several ADC references and is therefore misleading. The less ambiguous term Total Unadjusted Error is preferred.
2. Total Adjusted Error is the difference between the Actual and Adjusted Straight-Line Transfer Function, accounting for INL plus Quantization Error. This term is redundant and potentially confusing with respect to Total Unadjusted Error and will not be used.
3. Code Error is the error between the ideal code and the current code. This is the only figure of merit that measures by the quantized output.

Instead of voltage. The code error is the Total Unadjusted in LSB, rounded to the nearest integer.

References:

1. J. Feddeler and Bill Lucas, 8/16 Bit Division Systems Engineering, Austin, Texas, Aplication Note AN2438/D 2/2003, Frescale Semiconductor, Inc, Motorola 2003, www.freescale.com
2. http://en.wikipedia.org

ADC Definitions and Specifications 4

Offset and Gain Error
Zero-Scale Errors and Full-Scale Errors can be used to calculate Offset and Gain Errors. These terms are used to define the performance on many industry-standard ADC’s but the definitions used vary and can be misleading or inconsistent.

1. Offset Error (EO), Adjusted Offset, or Zero-Scale Offset is the difference between the actual and ideal first transition voltages. This is the same definition as Zero-Scale Error. The term offset; however, implies that all conversions are off by an equal amount. In the case of a strong non-linearity near the Zero-Scale Value, this definition may be misleading, and the less ambiguous Zero-Scale Error term is preferable.
2. Best-Fit Offset is the difference between the Best-Fit Straight-Line Transfer Function and the Ideal Straight-Line Transfer Function at VREFL. Some definitions define the offset point at the center-conversion ((VREFH – VREFL) /2) instead of at VREFL. This offset is virtually impossible to measure in the application and is therefore only a laboratory curiosity. Since this yields optimistic results and is not measurable in the application, it can be misleading and will not be used.
3. Full-Scale Offset is the difference between the actual and ideal last transition voltages. This is the same definition as Full-Scale Error, and is misleading for the same reason that Offset is misleading with respect to Zero-Scale Error.
4. Gain Error (EG) or Adjusted Gain Error is the difference in the slope of the Actual and the Ideal Straight-Line Transfer Functions. The error is not measured as a slope but rather as the difference in the total available input range from the first to the last conversions between the Ideal and Adjusted Straight-Line Transfer Functions. It is can also be expressed by: EG = EZS – EFS. Gain Error is not directly measurable and the term has been inconsistently defined in the literature. Additionally, if there are strong non-linearities at the endpoints, this definition of Gain Error may be misleading, so the less ambiguous Full-Scale Error term is preferred provided a simple gain calculation (above) is possible.
5. Best-Fit Gain Error is the difference in the slope of the Best-Fit and Ideal Straight-Line Transfer Functions. The error is not measured as a slope but rather as the difference in the total available input range from the first to the last conversions between the Ideal and Best-Fit Straight-Line Transfer Functions. Since the Best-Fit Straight-Line Transfer Function will result in an optimistic Gain Error and is virtually impossible to measure in the application, it can be misleading and will not be used.

Consistency with previous Freescale documents can be achieved by replacing references to Offset Error with Zero-Scale Error and Gain Error with the difference between of Zero Scale Errors and Full-Scale Errors.

Differential Non-Linearity (DNL)
Differential Non-Linearity (DNL) is the maximum of the differences in the each conversion’s Current Code Width (CCW) and the Ideal Code Width (ICW). DNL is the most critical of the measures of an ADC’s performance for many control applications since it represents the ADC’s ability to relate a small change in input voltage to the correct change in code conversion. DNL is defined as:

Code DNL = CCW – ICW
DNL = Max (Code DNL)

Some literature defines DNL using the Adjusted Code Width (ACW), which means Zero- and Full-Scale Error have been adjusted for. For relatively accurate ADC’s, the difference with respect to DNL is negligible, but using the ACW complicates defining and testing DNL. Additionally, this definition is only valid if the application has trim capability.


Related to DNL are two critical figures of merit used in defining ADC operation.
These are:

1. Missing Codes — An ADC has missing codes if an infinitesimally small change in voltage causes a change in result of two codes, with the intermediate code never being set. A DNL of –1.0 LSB indicates the ADC has missing codes (DNL measured by this definition cannot be less than –1.0 LSB).
2. Monotonicity — An ADC is monotonic if it continually increases conversion result with an increasing voltage (and vice versa). A nonmonotonic ADC may give a lower conversion result for a higher input voltage, which may also mean that the same conversion may result from two separate voltage ranges. Often, the transfer function will completely miss the lower code until after the higher code is converted (on an increasing input voltage).

Some literature suggests that a DNL of greater than 1.0 LSB may indicate nonmonotonicity. Non-monotonicity is usually accompanied by large, positive DNL (>1.0 LSB), although a non-monotonic situation can be coincident with a DNL of less than 1.0 LSB.

ADC Definitions and Specifications 3

Best-Fit Transfer Function
Some ADC’s exhibit low Zero- and Full-Scale Errors but still have significant non-linearities. In cases where these linearities tend to be in one direction (for example, a significantly “bowed” function) the best application results may be obtained if the errors are compared to a Best-Fit Transfer Function. The Best-Fit Straight-Line Transfer Function is the line from which the average deviation of all conversions is minimum. Computing this function requires that the entire Actual Transfer Function be recorded, which is impractical in most applications. Therefore, any performance parameters calculated against the Best-Fit Transfer Function are not useful to the user. Unfortunately, many automatic evaluation packages (software and hardware) assume this type of curve.

Zero-Scale Error and Full-Scale Error
The non-linearities at the endpoints are considered special cases due to the ease with which they are measured and corrected. The non-linearity at the beginning of the Actual Transfer Function is called the Zero-Scale Error (EZS) and the non-linearity at the top end of the function is called Full-Scale Error (EFS). The Zero- and Full-Scale Errors have the following definitions:

1. Zero-Scale Error (EZS) is the difference between actual first transition voltage and the ideal first transition voltage (if the first transition is not from $000 to $001, then use the difference between the actual and ideal $001–$002 transition voltages, and so on).

NOTE: The Ideal Code Width for the zero code is ½LSB for ADC’s with ½LSB compensated quantization.

Representing this error is by code widths: EZS = CCW(0) – ICW(0)
Or, in the case where the first “x” codes are missing, EZS = CCW(x) – sum(i=0 →x)[ICW(i)]

1. Full-Scale Error (EFS) is the difference between the actual last transition voltage and the ideal last transition voltage (if the last transition is not from $3FE to $3FF, then use the difference between the actual and ideal $3FD–$3FE transition voltages, and so on).

NOTE: The Ideal Code Width for the last code is 1½LSB for ADC’s with ½LSB compensated quantization.

Representing this error by code widths:
EFS = CCW(last) – ICW(last)
Or, in the case where the last “x” codes are missing,
EFS = CCW(last-x) – sum(i=x→last)[ICW(i)]

References:

1. J. Feddeler and Bill Lucas, 8/16 Bit Division Systems Engineering, Austin, Texas, Aplication Note AN2438/D 2/2003, Frescale Semiconductor, Inc, Motorola 2003, www.freescale.com
2. http://en.wikipedia.org

ADC Definitions and Specifications 2

Ideal Transfer Function
The Ideal Straight-Line Transfer Function of an ADC is a straight line from the minimum input voltage (voltage reference low; VREFL) to the maximum input voltage (voltage reference high; VREFH). The Ideal Transfer Function is then quantized (divided into steps) by the number of codes the ADC is capable of resolving. The input voltage range is divided into steps, each step having the same width.

This Ideal Code Width (ICW) — also known as 1LSB — is:
ICW = 1LSB = (VREFH – VREFL)/2N

Where:
N is the “width” of the ADC, in our examples, 10 bits.

The Ideal Transfer Function is then:
Code = (VIN – VREFL) / 1LSBVIN = (Code*1LSB) + VREFL

Quantization Error (EQ) and Method
The way the Ideal transfer function is divided into steps depends on the method of quantization the ADC uses. The two possible methods are:

1. Uncompensated Quantization — The first step is taken at 1LSB, with each successive step taken at 1LSB intervals and the last step taken at VREFH – 1LSB. The Quantization Error (EQ) in this case is from 0LSB to 1LSB.
2. ½LSB Compensated Quantization – The first step is taken at 1⁄2LSB, with each successive step taken at 1LSB intervals and the last step taken at VREFH – 11⁄2LSB. The Quantization Error (EQ) in this case is ±1⁄2LSB

Adjusted Transfer Function
Most ADC’s exhibit some non-linearity at the endpoints due to the difficulty in measuring a signal that is identical to the reference. If these errors are accounted for, a more accurate portrayal of the ADC behavior in application is possible. For this reason, the Adjusted Straight-Line Transfer Function is drawn between the minimums input voltage plus the Zero-Scale Error (VREFL + EZS) to the maximum input voltage plus the Full- Scale Error (VREFH + EFS).

The Adjusted Transfer Function is then quantized in the same method as the Ideal Transfer Function. The Adjusted Code Width is therefore:
ACW = [(VREFH + EFS) – (VREFL + EZS)] / 2N

The Adjusted Transfer Function is then:
Code = (VIN – VREFL – EZS) / ACW VIN = (Code*ACW) + VREFL + EZS

ADC Definitions and Specifications-1

Introduction
This application note will help users of analog-to-digital converters (ADC) understand common terminologies used in the electronics industry to define ADC operation and performance. There are many terms and parameters used to define the performance of ADC’s. Included in this document are common definitions, numerical specifications, differences, and issues with the definitions. By understanding the terminology used to specify various ADC parameters, a systems designer can better understand how to obtain the greatest overall system performance, based on the various performance features of any given ADC system.

Terms and Definitions
The following terms are used in the electronics industry to define ADC operation.

Measurement Units
There are several terms commonly used to measure ADC performance. Improper or inconsistent use of terms may result in confusion and or misinterpretation of performance. Common measurement units in use in the industry are described here (The following examples assume a 10-bit, 5.12-V ADC with an ideal 2.56-V conversion at $200):

Volts (V) — The error voltage is the difference between the input voltage that converts to a given code and the ideal input voltage for the same code. When the error is measured in volts, it is related to the actual voltages and is not normalized to or dependent on the input range or voltage supply. This measure is useful for fixed error sources such as offset but does not relate well to the observed error.

Least Significant Bits (LSB) — A least significant bit (LSB) is a unit of voltage equal to the smallest resolution of the ADC. This unit of measure approximately relates the error voltage to the observed error in conversion (code error), and is useful for systemic errors such as differential non-linearity. A 2.56-V input on an ADC with ± 3 LSB of error could read between $1FD and $203. This unit is by far the most common terminology and will be the preferred unit used for error representation.

Percent Full-Scale Value (%FSV) — Percent full-scale voltage is a unit of voltage equal to 1/100th of the input range of the ADC. This unit of error clarifies the size of the error relative to the input range, and is useful for trimmable errors such as offset or gain errors. This unit is difficult to accurately translate to observed error.

Counts — A count is a unit of voltage equal to an LSB. It is a terminology unique to specifications of some Freescale ADC’s and may be confusing to customers when doing cross-vendor comparisons.

Bits — A bit is a unit equal to the log (base2) of the error voltage normalized to the resolution of the ADC. An error of N bits corresponds to 2N LSB of error. This measure is easily confused with LSB and is hard to extrapolate between integer values.

Decibels (db) — A decibel is a unit equal to 20 times the log (base10) of the error voltage normalized to the full-scale value (20*log(err_volts/input_range)). A 2.56 input on an ADC with an error of 50 db will convert between $1FD and $203. This figure is often used in the communications field and is infrequently used in control or monitoring applications.

ADC Transfer Curves
The ADC converts an input voltage to a corresponding digital code. The curve describing this behavior is the Actual Transfer Function. The Ideal Transfer Function represents this behavior assuming the ADC is perfectly linear, or that a given change in input voltage will create the same change in conversion code regardless of the input’s initial level. The Adjusted Transfer Function assumes this behavior after the errors at the endpoint are accounted for.


References:

1. J. Feddeler and Bill Lucas, 8/16 Bit Division Systems Engineering, Austin, Texas, Aplication Note AN2438/D 2/2003, Frescale Semiconductor, Inc, Motorola 2003, www.freescale.com
2. http://en.wikipedia.org

Interfacing ADC0808 to 8051

Written by Amol Shah, on Jul-2008

In lot of embedded systems microcontrollers needs to take analog input. Most of the sensors & transducers such as temperature, humidity, pressure, are analog. For interfacing these sensors to microcontrollers we require to convert the analog output of these sensors to digital so that the controller can read it. Some microcontrollers have built in Analog to Digital Converter (ADC) so there is no need of external ADC. For microcontrollers that don’t have internal ADC external ADC is used. One of the most commonly used ADC is ADC0808. ADC 0808 is a Successive approximation type with 8 channels i.e. it can directly access 8 single ended analog signals.

I/O Pins
ADDRESS LINE A, B, C
The device contains 8-channels. A particular channel is selected by using the address decoder line. The TABLE 1 shows the input states for address lines to select any channel.

Address Latch Enable ALE
The address is latched on the Low – High transition of ALE.

START
The ADC’s Successive Approximation Register (SAR) is reset on the positive edge i.e. Low- High of the Start Conversion pulse. Whereas the conversion is begun on the falling edge i.e. High – Low of the pulse.

Output Enable
Whenever data has to be read from the ADC, Output Enable pin has to be pulled high thus enabling the TRI-STATE outputs, allowing data to be read from the data pins D0-D7.

End of Conversion (EOC)
This Pin becomes High when the conversion has ended, so the controller comes to know that the data can now be read from the data pins.

Clock
External clock pulses are to be given to the ADC; this can be given either from LM 555 in Astable mode or the controller can also be used to give the pulses.

ALGORITHM
Start.
Select the channel.
A Low – High transition on ALE to latch in the address.
A Low – High transition on Start to reset the ADC’s SAR.
A High – Low transition on ALE.
A High – Low transition on start to start the conversion.
Wait for End of cycle (EOC) pin to become high.
Make Output Enable pin High.
Take Data from the ADC’s output
Make Output Enable pin Low.

The total numbers of lines required are:
Data lines: 8
ALE: 1
START: 1
EOC: 1
Output Enable: 1

I.e. total 12 lines. You can directly connect the OE pin to Vcc. Moreover instead of polling for EOC just put some delay so instead of 12 lines you will require 10 lines. You can also provide the clock through the controller thus eliminating the need of external circuit for clock.

Calculating Step Size
ADC 0808 is an 8 bit ADC i.e. it divides the voltage applied at Vref+ & Vref- into 28 i.e. 256 steps.

Step Size = (Vref+ - Vref-)/256

Suppose Vref+ is connected to Vcc i.e. 5V & Vref- is connected to the Gnd then the step size will be

Step size= (5 - 0)/256= 19.53 mv.

Calculating Dout.
The data we get at the D0 - D7 depends upon the step size & the Input voltage i.e. Vin.
Dout = Vin /step Size.
If you want to interface sensors like LM35 which has output 10mv/°C then I would suggest that you set the Vref+ to 2.56v so that the step size will be

Step size= (2.56 - 0)/256= 10 mV.

So now whatever reading that you get from the ADC will be equal to the actual temperature.

PROGRAM
Here is a program for interfacing the ADC to microcontroller, as stated above I have assumed that the OE pin is connected to Vcc & the clock is given by the controller. This program selects channel 0 as input channel reads from it & saves in the accumulator.
adc_a bit p2.0
adc_b bit p2.1
adc_c bit p2.2
adc_start bit p2.3
adc_ale bit p2.4
adc_clk bit P2.5

Org 0000h
clr ale
clr start

clr adc_a ;
clr adc_b ;Select Channel 0
clr adc_c ;
call delay_small
setb adc_ale ;ale pin high
call delay_small
setb adc_start ;start pin high
call delay_small
clr adc_ale ;ale pin low
call delay_small
clr adc_start ;start pin low
call delay_long
mov a,P1
loop:
ajmp loop

delay_small:
mov r0,#10
l1_delay_small:
cpl adc_clk
nop
nop
nop
nop
nop
nop
djnz r0,l1_delay_small
ret

delay_long:
mov r0,#40
l1_delay_long:
cpl adc_clk
nop
nop
nop
nop
nop
djnz r0,l1_delay_long
ret

End

References:

1. http://www.dnatechindia.com/
2. http://en.wikipedia.org

Counting Type ADCs - 3

Analog to Digital Converts
By Ibrahim Kamal

The Software
The software to be loaded on a microcontroller to perform the task of converting analog signals to digital ones is very simple; The pins P3.0 and P3.1 are both set to Logic 0, and the value of port 2 (which is connected to the first 8 bits of the DAC) is gradually incremented. After each increment the pin P3.7 is checked. Whenever P3.7 is low (logic 0) that means that the generated Analog signal corresponds (with one bit accuracy) to the measured analog signal, and consequently corresponds to the last counted digital value in the micro-controller. In order to extend the resolution from 8 bits to 10 bits, the value of the pins P3.0 and P3.1 is increased each time Port 2 overflows. This way, the precision of this converter is 5 / 1024 = 0.005V, and you can freely increase the precision by increasing the number of bits.

Here is an example C code for the 8051 micro-controller to read the voltage from the above schematic.

While (1){
done = 0;
P3_0 = 0;
P3_1 = 0;
P3_7 = 1; //set P3_7 as input
P2 = 0; //Start counting from 0
delay(100);
while (P2 < 255){
P2++;
delay(100); //Slow down the process, to be compatible with
if (P3_7 == 1){ //the response time of the Op-Amp.
done = 1;
break;
}
}
if (done == 0){
P3_0 = 1;
P3_1 = 0;
P3_7 = 1;
P2 = 0;
while (P2 < 255){
P2++;
delay(100);
if (P3_7 == 1){
done = 1;
break;
}
}
}
if (done == 0){
P3_0 = 0;
P3_1 = 1;
P3_7 = 1;
P2 = 0;
while (P2 < 255){
P2++;
delay(100);
if (P3_7 == 1){
done = 1;
break;
}
}
}
if (done == 0){
P3_0 = 1;
P3_1 = 1;
P3_7 = 1;
P2 = 0;
while (P2 < 255){
P2++;
delay(100);
if (P3_7 == 1){
done = 1;
break;
}
}
}
if (done == 1){
bit8 = P3_0;
bit9 = P3_1;
voltage = ((P2 + (bit8 * 256) + (bit9 * 512))*conversion_factor);
}

The variable 'conversion_factor' in the code represent a factor that relates the counted value to the corresponding voltage, and is easily obtained using some trials and errors. Noting that the relation between the counted value and the corresponding voltage is linear, it's easy to find this factor based on only 2 readings.

References:

1. Counting Type ADC, Analog to Digital Converter, http://www.ikalogic.com/
2. http://en.wikipedia.org

Counting Type ADCs - 2

Analog to Digital Converts
By Ibrahim Kamal

The Electronic circuit
Any Experienced reader may have noticed that the hardware for such a device is very simple (with disregard to the microcontroller). Indeed, you only need to slightly change the design of the DAC explained in this early tutorial. The components on the left part of the schematic are standard in most of the projects, which are the capacitors (C1 and C2), the crystal oscillator (X1), the reset switch (SW1) with the debouncing capacitor (C3) and resistor (R12), and the connector (J1) for ISP programming. The resistor R13 to R32 and LM358 comparator are responsible of converting Digital signals to Analog signals with 10 bits resolution, and adding to that a micro-controller, we get an ADC.

As mentioned before, the purpose of a micro-controller in this application is to generate the analog signals to be compared with the measured input voltage (Vin). The LM358 comparator will give a change of logic level (from 0 to 1) indicating that the simulated analog voltage reached the measured voltage, thus indicating the end of conversion.

References:

1. Counting Type ADC, Analog to Digital Converter, http://www.ikalogic.com/
2. http://en.wikipedia.org

Counting Type ADCs - 1

Analog to Digital Converts
By Ibrahim Kamal

Overview In this article, we will discuss a very common type of digital to analog converters called the counting type ADC. Based on our previous simple tutorial about DACs (digital to analog converters), this article presents a technique of building ADCs that you can use to learn and master the process of analog to digital conversion, but also use it in many of you projects, adding an incredible feature to basic microcontrollers like the 8051 that don't have integrated ADCs.

The principle of operation
While there are many ways of building and implementing a counting type ADC, they all rely on the same basic idea. I am going to use a micro-controller by default to perform all the required logical operations, because in most cases, where an ADC is found, a microcontroller is also present. As you can see in figure 1A, the counting type ADC is based on Digital to analog converter (DAC). An R/2R DAC is very suitable for this task, and it can offer more precision by adding more branches to the R/2R network, consequently adding more bit depth to the converter, or you may call it "more resolution". To understand how an analog input is converted to digital data, you have to think in the reverse direction, because that's what really happens, the microcontroller tries to mimic the analog input by producing the closest analog input through the DAC. More precisely.

Fig. 1A: Principle of operation of a counting type ADC

The microcontroller generates a digital ramp (a signal increasing from 0 to max scale) on the input of the DAC, which in case of an 8-bit DAC with a 5V maximum output voltage, would be a counting from 0 to 255, generating an increasing analog voltage (0v to 5V) at the output of the DAC, which is then fed to a comparator to be compared with analog input signal being converted.

Fig. 1B: Principle of operation of a counting type ADC

While the analog output voltage from the DAC is smaller than the measured input, the comparator will output logic 0. Once the DAC output a voltage that is slightly bigger than the analog input, the comparator will output logic 1 indicating the end of the conversion (refereed to as EOC). The job of the microcontroller is to monitor the output of the comparator, and record the value of the data that was sent to the DAC just before, or just after the comparator' output flipped form 0 to 1. Figure 1B may help you to imagine the relation between the 3 major signals: The analog input being measured, the Analog output from the DAC and the EOC signal. The resolutions - which are the smallest change in the input that can be detected - depend on the number of data line 'n'. That means that you can build your own ADC with any precision you may need. That becomes interesting sometimes when you need very low or very high precision ADCs.


References:

1. Counting Type ADC, Analog to Digital Converter, http://www.ikalogic.com/
2. http://en.wikipedia.org

Understanding ADC Specifications 10

By Len Staller
Embedded Systems Design
(02/24/05, 05:24:00 PM EST)

Reading ADC Specification NumbersThe ADC specifications posted in data sheets serve to define the performance of an ADC in different types of applications. The engineer uses these specifications to define if, how, and in what way the ADC should be used in an application. Performance specifications can also be a guarantee that an ADC will perform in a certain way. If a specification is labeled as a maximum or minimum, this is implied. For example, in the ADC specification shown in Table 1, the data sheet excerpt gives an INL error maximum of 1 LSB. This should mean the manufacturer has tested the ADC and is stating that INL error should not be greater or less than 1 LSB. Besides minimum and maximum, specifications listed as typical are also given. This is not a guarantee but simply represents typical performance for that ADC. For example, if a data sheet specifies 2 LSB INL in the "Typical" column, there's no implied guarantee that the engineer won't find the ADC with higher INL error.

Though a typical number is not a guarantee, it should give the designer an idea of how the ADC will perform, since these numbers are generally derived from the manufacturer's characterization data or are expected by design. Typical numbers are more helpful when the manufacturer gives the standard deviation from the mean of the tested specification. This gives the engineer more information on how the ADC's performance can be expected to deviate from the numbers posted as typical. Keep this in mind when comparing ADC data sheets, especially if the specification is critical to your design. An ADC with a typical 2 LSB INL may yield higher INL error than expected, making a 12-bit ADC effectively a 10-bit ADC—caveat emptor!

Len Staller serves as an applications engineer for Silicon Laboratories' microcontroller products. Previously, he was an applications engineer for Cygnal Integrated Products, which was acquired by Silicon Laboratories in 2003. Staller has a bachelor's degree in electrical engineering from The University of Texas at Austin. He can be reached at Len.Staller@silabs.com.

Reference:

1. http://www.embended.com/
2. http://en.wikipedia.org

Understanding ADC Specifications 9

By Len Staller
Embedded Systems Design
(02/24/05, 05:24:00 PM EST)

Signal-to-noise and distortion
Signal-to-noise and distortion (SiNAD) offers a more complete picture by including the noise and harmonic distortion in one specification. SiNAD gives a description of how the measured signal will compare to the noise and distortion. You can calculate the SiNAD ratio using Equation 6.

SiNAD = 20 log | V1 / √V22 + V23 + … + V2n + V2noise
(Equation 6)

Spurious-free dynamic range
Finally, spurious-free dynamic range (SFDR) is the difference between the magnitude of the measured signal and its highest spur peak. This spur is typically a harmonic of the measured signal but doesn't have to be. SFDR is shown in Figure 11.

Figure 11: Spurious-free dynamic range (SFDR)

Reference:

1. http://www.embended.com/
2. http://en.wikipedia.org

Understanding ADC Specifications 8

By Len Staller
Embedded Systems Design
(02/24/05, 05:24:00 PM EST)

Harmonic distortion
Nonlinearity in the data converter results in harmonic distortion when analyzed in the frequency domain. Such distortion is observed as "spurs" in the FFT at harmonics of the measured signal as illustrated in Figure 10. This distortion is referred to as total harmonic distortion (THD), and its power is calculated in Equation 5.

Figure 10: FFT showing harmonic distortion

THD = 20 log | √V22 + V22 + … + V2n / V1| (Equation 5)

The magnitude of harmonic distortion diminishes at high frequencies to the point that its magnitude is less than the noise floor or is beyond the bandwidth of interest. Data sheets typically specify to what order the harmonic distortion has been calculated. Manufacturers will specify which harmonic is used in calculating THD; for example, up to the fifth harmonic is common (see the example ADC specification in Table 1).

Table 1: Example: Silicon Labs C8051F060 16-bit ADC electrical characteristics

Reference:

1. http://www.embended.com/
2. http://en.wikipedia.org

Understanding ADC Specifications 7

By Len Staller
Embedded Systems Design
(02/24/05, 05:24:00 PM EST)

Signal-to-noise ratio
The signal-to-noise ratio (SNR) is the ratio of the root mean square (RMS) power of the input signal to the RMS noise power (excluding harmonic distortion), expressed in decibels (dB), as shown in Equation 3.

SNR(dB) = 20 log | Vsignal (rms) / V noise (rms) (Equation 3)

SNR is a comparison of the noise to be expected with respect to the measured signal. The noise measured in an SNR calculation doesn't include harmonic distortion but does include quantization noise (an artifact of quantization error) and all other sources of noise (for example, thermal noise). This noise floor is depicted in the FFT plot in Figure 9. For a given ADC resolution, the quantization noise is what limits an ADC to its theoretical best SNR because quantization error is the only error in an ideal ADC. The theoretical best SNR is calculated in Equation 4.

Figure 9: SNR— A measure of the signal compared to the noise floor

SNR(dB) = 6.02N + 1.76 (4) (Equation 4)
Where N is the ADC resolution

Quantization noise can only be reduced by making a higher-resolution measurement (in other words, a higher-resolution ADC or oversampling). Other sources of noise include thermal noise, 1/ƒ noise, and sample clock jitter.


Reference:

1. http://www.embended.com/
2. http://en.wikipedia.org

Understanding ADC Specifications 6

By Len Staller
Embedded Systems Design
(02/24/05, 05:24:00 PM EST)

Absolute error
The absolute error is the total DC measurement error and is characterized by the offset, full-scale, INL, and DNL errors. Quantization error also affects accuracy, but it's inherent in the analog-to-digital conversion process (and so does not vary from one ADC to another of equal resolution). When designing with an ADC, the engineer uses the performance specifications posted in the data sheet to calculate the maximum absolute error that can be expected in the measurement, if it's important. Offset and full-scale errors can be reduced by calibration at the expense of dynamic range and the cost of the calibration process itself. Adding or subtracting a constant number to or from the ADC output codes can minimize offset error. Multiplying the ADC output codes by a correction factor can minimize full-scale error. Absolute error is less important in some applications, such as closed-loop control, where DNL is most important.

Dynamic performance
An ADC's dynamic performance is specified using parameters obtained via frequency-domain analysis and is typically measured by performing a fast Fourier transform (FFT) on the output codes of the ADC. In Figure 8, the fundamental frequency is the input signal frequency. This is the signal measured with the ADC. Everything else is noise—the unwanted signals—to be characterized with respect to the desired signal. This includes harmonic distortion, thermal noise, 1/ƒ noise, and quantization noise. (The figure is exaggerated for ease of observation.) Some sources of noise may not derive from the ADC itself. For example, distortion and thermal noise originate from the external circuit at the input to the ADC. Engineers minimize outside sources of error when assessing the performance of an ADC and in their system design.

Figure 8: An FFT of ADC output codes

Reference:

1. http://www.embended.com/
2. http://en.wikipedia.org

Understanding ADC Specifications 5

By Len Staller

Embedded Systems Design
(02/24/05, 05:24:00 PM EST)

Non-linearity
Ideally, each code width (LSB) on an ADC's transfer function should be uniform in size. For example, all codes in Figure 2 should represent exactly 1/8th of the ADC's full-scale voltage reference. The difference in code widths from one code to the next is differential nonlinearity (DNL). The code width (or LSB) of an ADC is shown in Equation 1.

LSB = Vref / 2N (Equation 1)

The voltage difference between each code transition should be equal to one LSB, as defined in Equation 1. Deviation of each code from an LSB is measured as DNL. This can be observed as uneven spacing of the code "steps" or transition boundaries on the ADC's transfer-function plot. In Figure 6, a selected digital output code width is shown as larger than the previous code's step size. This difference is DNL error. DNL is calculated as shown in Equation 2.

Figure 6: Differential nonlinearity

DNL = (Vn+1 – Vn) / VLSB (Equation 2)

The integral nonlinearity (INL) is the deviation of an ADC's transfer function from a straight line. This line is often a best-fit line among the points in the plot but can also be a line that connects the highest and lowest data points, or endpoints. INL is determined by measuring the voltage at which all code transitions occur and comparing them to the ideal. The difference between the ideal voltage levels at which code transitions occur and the actual voltage is the INL error, expressed in LSBs. INL error at any given point in an ADC's transfer function is the accumulation of all DNL errors of all previous (or lower) ADC codes, hence it's called integral nonlinearity. This is observed as the deviation from a straight-line transfer function, as shown in Figure 7.

Figure 7: Integral nonlinearity error

Because nonlinearity in measurement will cause distortion, INL will also affect the dynamic performance of an ADC.

Reference:

1. http://www.embended.com/
2. http://en.wikipedia.org

Understanding ADC Specifications 4

By Len Staller
Embedded Systems Design
(02/24/05, 05:24:00 PM EST)

Offset error, full-scale error
The ideal transfer function line will intersect the origin of the plot. The first code boundary will occur at 1 LSB as shown in Figure 1. You can observe offset error as a shifting of the entire transfer function left or right along the input voltage axis, as shown in Figure 3.

Figure 3: Offset error

An error of - 1/2 LSB is intentionally introduced into some ADCs but is still included in the specification in the data sheet. Thus, the offset-error specification posted in the data sheet includes 1/2 LSB of offset by design. This is done to shift the potential quantization error in a measurement from 0 to 1 LSB to - 1/2 to +1/2 LSB. In this way, the magnitude of quantization error is intended to be < style="text-align: center;">

Figure 4: Quantization error vs. output code

Figure 5: Full-scale error

Full-scale error is the difference between the ideal code transition to the highest output code and the actual transition to the output code when the offset error is zero. This is observed as a change in slope of the transfer function line as shown in Figure 5. A similar specification, gain error, also describes the non-ideal slope of the transfer function as well as what the highest code transition would be without the offset error. Full-scale error accounts for both gain and offset deviation from the ideal transfer function. Both full-scale and gain errors are commonly used by ADC manufacturers.

Reference:

1. http://www.embended.com/
2. http://en.wikipedia.org

Understanding Analog to Digital Converter Specifications 3

By Len Staller
Embedded Systems Design
(02/24/05, 05:24:00 PM EST)

The ideal transfer function
The transfer function of an ADC is a plot of the voltage input to the ADC versus the code's output by the ADC. Such a plot is not continuous but is a plot of 2N codes, where N is the ADC's resolution in bits. If you were to connect the codes by lines (usually at code-transition boundaries), the ideal transfer function would plot a straight line. A line drawn through the points at each code boundary would begin at the origin of the plot, and the slope of the plot for each supplied ADC would be the same as shown in Figure 1.

Figure 1: Ideal transfer function of a 3-bit ADC

Figure 1 depicts an ideal transfer function for a 3-bit ADC with reference points at code transition boundaries. The output code will be its lowest (000) at less than 1/8 of the full-scale (the size of this ADC's code width). Also, note that the ADC reaches its full-scale output code (111) at 7/8 of full scale, not at the full-scale value. Thus, the transition to the maximum digital output does not occur at full-scale input voltage. The transition occurs at one code width—or least significant bit (LSB)—less than full-scale input voltage (in other words, voltage reference voltage).

Figure 2: 3-bit ADC transfer function with - 1/2 LSB offset

The transfer function can be implemented with an offset of - 1/2 LSB, as shown in Figure 2. This shift of the transfer function to the left shifts the quantization error from a range of (- 1 to 0 LSB) to (- 1/2 to +1/2 LSB). Although this offset is intentional, it's often included in a data sheet as part of offset error (see section on offset error). Limitations in the materials used in fabrication mean that real-world ADCs won't have this perfect transfer function. It's these deviations from the perfect transfer function that define the DC accuracy and are characterized by the specifications in a data sheet. The DC performance specifications described have accompanying figures that depict two transfer function segments: the ideal transfer function (solid, blue lines) and a transfer function that deviates from the ideal with the applicable error described (dashed, yellow line). This is done to better illustrate the meaning of the performance specifications.

Reference:

1. http://www.embended.com/
2. http://en.wikipedia.org

Understanding Analog to Digital Converter Specifications 2

By Len Staller
Embedded Systems Design
(02/24/05, 05:24:00 PM EST)

DC accuracy
Many signals remain relatively static, such as those from temperature sensors or pressure transducers. In such applications, the measured voltage is related to some physical measurement, and the absolute accuracy of the voltage measurement is important. The ADC specifications that describe this type of accuracy are offset error, full-scale error, differential nonlinearity (DNL), and integral nonlinearity (INL). These four specifications build a complete description of an ADC's absolute accuracy.

Although not a specification, one of the fundamental errors in ADC measurement is a result of the data-conversion process itself: quantization error. This error cannot be avoided in ADC measurements. DC accuracy, and resulting absolute error are determined by four specs—offset, full-scale/gain error, INL, and DNL. Quantization error is an artifact of representing an analog signal with a digital number (in other words, an artifact of analog-to-digital conversion). Maximum quantization error is determined by the resolution of the measurement (resolution of the ADC, or measurement if signal is oversampled). Further, quantization error will appear as noise, referred to as quantization noise in the dynamic analysis. For example, quantization error will appear as the noise floor in an FFT plot of a measured signal input to an ADC, which I'll discuss later in the dynamic performance section).

Reference:

1. http://www.embended.com/
2. http://en.wikipedia.org

Understanding Analog to Digital Converter Specifications 1

By Len Staller
Embedded Systems Design
(02/24/05, 05:24:00 PM EST)

Confused by analog-to-digital converter specifications? Here's a primer to help you decipher them and make the right decisions for your project.

Although manufacturers use common terms to describe analog-to-digital converters (ADCs), the way ADC makers specify the performance of ADCs in data sheets can be confusing, especially for a newcomers. But to select the correct ADC for an application, it's essential to understand the specifications. This guide will help engineers to better understand the specifications commonly posted in manufacturers' data sheets that describe the performance of successive approximation register (SAR) ADCs.

ABCs of ADCs
ADCs convert an analog signal input to a digital output code. ADC measurements deviate from the ideal due to variations in the manufacturing process common to all integrated circuits (ICs) and through various sources of inaccuracy in the analog-to-digital conversion process. The ADC performance specifications will quantify the errors that are caused by the ADC itself.

ADC performance specifications are generally categorized in two ways: DC accuracy and dynamic performance. Most applications use ADCs to measure a relatively static, DC-like signal (for example, a temperature sensor or strain-gauge voltage) or a dynamic signal (such as processing of a voice signal or tone detection). The application determines which specifications the designer will consider the most important.

For example, a DTMF decoder samples a telephone signal to determine which button is depressed on a touchtone keypad. Here, the concern is the measurement of a signal's power (at a given set of frequencies) among other tones and noise generated by ADC measurement errors. In this design, the engineer will be most concerned with dynamic performance specifications such as signal-to-noise ratio and harmonic distortion. In another example, a system may measure a sensor output to determine the temperature of a fluid. In this case, the DC accuracy of a measurement is prevalent so the offset, gain, and non-linearity will be most important.

Reference:

1. http://www.embended.com/
2. http://en.wikipedia.org

Time Stretch Analog to Digital Converter (TS-ADC)

Time-stretch analog-to-digital converter (TS-ADC) is an analog-to-digital converter (ADC) system that has the capability of digitizing very high bandwidth signals that cannot be captured by conventional electronic ADCs. Alternatively, it is also known as the Photonic Time Stretch (PTS) digitizer, since it uses an optical frontend. It relies on the process of time-stretch, which effectively slows down the analog signal in time (or compresses its bandwidth) before a slow electronic ADC can digitize it.

Background
There is a huge demand for very high-speed analog-to-digital converters (ADCs), as they are needed for test and measurement equipment in laboratories and in high speed data communications systems. Most of the ADCs are based purely on electronic circuits, which have limited speeds and add a lot of impairments, limiting the bandwidth of the signals that can digitized and the achievable signal-to-noise ratio. In the TS-ADC, this limitation is overcome by time-stretching the analog signal, which effectively slows down the signal in time prior to digitization. By doing so, the bandwidth (and carrier frequency) of the signal is compressed. Electronic ADCs that would have been too slow to digitize the original signal, can now be used to capture this slowed down signal.

How it works

Fig. 1 A time-stretch analog-to-digital converter (with a stretch factor of 4) is shown. The original analog signal is time-stretched and segmented with the help of a time-stretch preprocessor (generally on optical frontend). Slowed down segments are captured by conventional electronic ADCs. The digitized samples are rearranged to obtain the digital representation of the original signal.

Fig. 2 Optical frontend for a time-stretch analog-to-digital converter is shown. The original analog signal is modulated over a chirped optical pulse (obtained by dispersing a ultra-short supercontinuum pulse). Second dispersive medium stretches the optical pulse further. At the photodetector (PD) output, stretched replica of original signal is obtained.

The basic operating principle of the TS-ADC is shown in Fig. 1. The time-stretch processor, which is generally an optical frontend, stretches the signal in time. It also divides the signal into multiple segments using a filter, for example a wavelength division multiplexing (WDM) filter, to ensure that the stretched replica of the original analog signal segments do not overlap each other in time after stretching. The time-stretched and slowed down signal segments are then converted into digital samples by slow electronic ADCs. Finally, these samples are collected by a digital signal processor (DSP) and rearranged in a manner such that output data is the digital representation of the original analog signal. Any distortion added to the signal by the time-stretch preprocessor is also removed by the DSP.

An optical frontend is commonly used to accomplish this process of time-stretch, as shown in Fig. 2. An ultrashort optical pulse (typically 100 to 200 femtoseconds long), also called a supercontinuum pulse, which has a broad optical bandwidth, is time-stretched by dispersing it in a highly dispersive medium (such as a dispersion compensating fiber). This process results in (an almost) linear time-to-wavelength mapping in the stretched pulse, because different wavelengths travel at different speeds in the dispersive medium. The obtained pulse is called a chirped pulse as its frequency is changing with time, and it is typically a few nanoseconds long. The analog signal is modulated onto this chirped pulse using an electro-optic intensity modulator. Subsequently, the modulated pulse is stretched further in the second dispersive medium which has much higher dispersion value. Finally, this obtained optical pulse is converted to electrical domain by a photodetector, giving the stretched replica of the original analog signal.

For continuous operation, a train of supercontinuum pulses is used. The chirped pulses arriving at the electro-optic modulator should be wide enough (in time) such that the trailing edge of one pulse overlaps the leading edge of the next pulse. For segmentation, optical filters separate the signal into multiple wavelength channels at the output of the second dispersive medium. For each channel, a separate photodetector and backend electronic ADC is used. Finally the outputs of these ADCs are passed on to the DSP, which generates the desired digital output.

Impulse response of the photonic time-stretch (PTS) system

Fig. 3 Capture of a 95-GHz RF tone using the photonic time-stretch digitizer. The signal is captured at an effective sample rate of 10-Terasamples-per-second.

The PTS processor is based on specialized analog optical (or microwave photonic) fiber links such as those used in cable TV distribution. While the dispersion of fiber is a nuisance in conventional analog optical links, time-stretch technique exploits it to slow down the electrical waveform in the optical domain. In the cable TV link, the light source is a continuous-wave (CW) laser. In PTS, the source is a chirped pulse laser.

In a conventional analog optical link, dispersion causes the upper and lower modulation sidebands, foptical ± felectrical, to slip in relative phase. At certain frequencies, their beats with the optical carrier interfere destructively, creating nulls in the frequency response of the system. For practical systems the first null is at tens of GHz, which is sufficient for handling most electrical signals of interest. Although it may seem that the dispersion penalty places a fundamental limit on the impulse response (or the bandwidth) of the time-stretch system, it can be eliminated. The dispersion penalty vanishes with single-sideband modulation. Alternatively, one can use the modulator’s secondary (inverse) output port to eliminate the dispersion penalty, in much the same way as two antennas can eliminate spatial nulls in wireless communication (hence the two antennas on top of a WiFi access point). Thus, the impulse response (bandwidth) of a time-stretch system is limited only by the bandwidth of the electro-optic modulator, which is about 120 GHz—a value that is adequate for capturing most electrical waveforms of interest.

Extremely large stretch factors can be obtained using long lengths of fiber, but at the cost of larger loss—a problem that has been overcome by employing Raman amplification within the dispersive fiber itself, leading to the world’s fastest real-time digitizer, as shown in Fig. 3. Also, using PTS, capture of very high frequency signals with a world record resolution in 10-GHz bandwidth range has been achieved.

Comparison with time lens imaging
Another technique, that involves a time lens, can also be used to slow down (mostly optical) signals in time. The time-lens concept relies on the mathematical equivalence between spatial diffraction and temporal dispersion, the so-called space-time duality. A lens held a fixed distance from an object produces a magnified image visible to the eye. The lens imparts a quadratic phase shift to the spatial frequency components of the optical waves; in conjunction with the free space propagation (object to lens, lens to eye), this generates a magnified image. Owing to the mathematical equivalence between paraxial diffraction and temporal dispersion, an optical waveform can be temporally imaged by a three-step process of dispersing it in time, subjecting it to a phase shift that is quadratic in time (the time lens itself), and dispersing it again. Theoretically, a focused aberration-free image is obtained under a specific condition when the two dispersive elements and the phase shift satisfy the temporal equivalent of the classic lens equation. Alternatively, the time lens can be used without the second dispersive element to transfer the waveform’s temporal profile to the spectral domain, analogous to the property that an ordinary lens produces the spatial Fourier transform of an object at its focal points.

In contrast to the time-lens approach, PTS is not based on the space-time duality – there is no lens equation that needs to be satisfied in order to obtain an error-free slowed-down version of the input waveform. Time-stretch technique also offers continuous-time acquisition performance, a feature needed for mainstream applications of oscilloscopes.
Another important difference between the two techniques is that the time lens requires the input signal to be subjected to high amount of dispersion before further processing. For electrical waveforms, the electronic devices that have the required characteristics: (1) high dispersion to loss ratio, (2) uniform dispersion, and (3) broad bandwidths, do not exist. This renders time lens not suitable for slowing down wideband electrical waveforms. In contrast, PTS does not have such a requirement. It was developed specifically for slowing down electrical waveforms and enable high-speed digitizers.

References:

1. A. S. Bhushan, F. Coppinger, and B. Jalali, “Time-stretched analogue-to-digital conversion," Electronics Letters vol. 34, no. 9, pp. 839-841, April 1998.
2. Y. Han and B. Jalali, “Photonic Time-Stretched Analog-to-Digital Converter: Fundamental Concepts and Practical Considerations," Journal of Lightwave Technology, Vol. 21, Issue 12, pp. 3085-3103, Dec. 2003.
3. J. Capmany and D. Novak, “Microwave photonics combines two worlds," Nature Photonics 1, 319-330 (2007).
4. J. Chou, O. Boyraz, D. Solli, and B. Jalali, “Femtosecond real-time single-shot digitizer," Applied Physics Letters 91, 161105 (2007).
5. S. Gupta and B. Jalali, “Time-warp correction and calibration in photonic time-stretch analog-to-digital converter," Optics Letters 33, 2674-2676 (2008).
6. B. H. Kolner and M. Nazarathy, “Temporal imaging with a time lens," Optics Letters 14, 630-632 (1989.
7. J. W. Goodman, “Introduction to Fourier Optics," McGraw-Hill (1968).
8. http://en.wikipedia.org